Skip to content

Commit 0396fe9

Browse files
authored
Update CMIS-custom-SI-settings.md
Address review comments
1 parent 8411546 commit 0396fe9

File tree

1 file changed

+83
-71
lines changed

1 file changed

+83
-71
lines changed

doc/sfp-cmis/CMIS-custom-SI-settings.md

+83-71
Original file line numberDiff line numberDiff line change
@@ -1,38 +1,43 @@
1-
# Feature Name
2-
Custom SI settings for CMIS modules
1+
# Custom SI settings for CMIS modules #
32

4-
# High Level Design Document
53
#### Rev 0.1
64

7-
# Table of Contents
8-
* [List of Tables](#list-of-tables)
9-
* [Revision](#revision)
10-
* [About This Manual](#about-this-manual)
11-
* [Abbreviation](#abbreviation)
12-
* [References](#references)
13-
* [Problem Definition](#problem-definition)
14-
* [Objective](#objective)
15-
* [Plan](#plan)
16-
* [Proposed Work-Flows](#proposed-work-flow)
17-
* [Feature Enablement](#feature-enablement)
18-
* [No Transceiver Present](#no-transceiver-present)
19-
* [Out Of Scope](#out-of-scope)
20-
21-
# List of Tables
5+
## Table of Contents
6+
- [List of Tables](#list-of-tables)
7+
- [Revision](#revision)
8+
- [Definition](#definition)
9+
- [References](#references)
10+
- [About This Manual](#about-this-manual)
11+
- [1 Introduction and Scope](#1-introduction-and-scope)
12+
- [1.1 Clause from CMIS5p0 spec for Signal Integrity](#11-clause-from-cmis5p0-spec-for-signal-integrity)
13+
- [1.2 Clause from CMIS5p0 spec for Explicit Control](#12-clause-from-cmis5p0-spec-for-explicit-control)
14+
- [2 Requirements](#2-requirements)
15+
- [3 Architecture Design](#3-architecture-design)
16+
- [3.1 TX_SETTING](#31-tx_setting)
17+
- [3.2 RX_SETTING](#32-rx_setting)
18+
- [3.3 GLOBAL_MEDIA_SETTINGS](#33-global_media_settings)
19+
- [3.4 PORT_MEDIA_SETTINGS](#34-port_media_settings)
20+
- [3.5 List of standard TX RX SI parameters](#35-list-of-standard-tx-rx-si-parameters)
21+
- [3.6 Sample Optics SI setting file](#36-sample-optics-si-setting-file)
22+
- [4 High-Level Design](#4-high-level-design)
23+
- [5 SAI API](#5-sai-api)
24+
- [6 Configuration and management](#6-configuration-and-management)
25+
- [7 Warmboot and Fastboot Design Impact](#7-warmboot-and-fastboot-design-impact)
26+
- [8 Restrictions or Limitations](#8-restrictions-or-limitations)
27+
- [9 Unit Test cases](#9-unit-test-cases)
28+
29+
### List of Tables
2230
* [Table 1: Definitions](#table-1-definitions)
2331
* [Table 2: References](#table-2-references)
2432

25-
# Revision
33+
### Revision
2634
| Rev | Date | Author | Change Description |
2735
|:---:|:-----------:|:----------------------------------:|-------------------------------------|
2836
| 0.1 | 05/05/2023 | Anoop Kamath | Initial version
2937

30-
# About this Manual
31-
This is a high-level design document describing the way to apply custom SI settings for CMIS supported modules
38+
### Definition
3239

33-
# Abbreviation
34-
35-
# Table 1: Definitions
40+
#### Table 1: Definitions
3641
| **Term** | **Definition** |
3742
| -------------- | ------------------------------------------------ |
3843
| xcvrd | Transceiver Daemon |
@@ -46,42 +51,44 @@ This is a high-level design document describing the way to apply custom SI setti
4651
| RX | Recieve |
4752
| EQ | Equalizer |
4853

49-
# References
54+
### References
5055

51-
# Table 2 References
56+
#### Table 2: References
5257

5358
| **Document** | **Location** |
5459
|---------------------------------------------------------|---------------|
5560
| CMIS v5 | [CMIS5p0.pdf](http://www.qsfp-dd.com/wp-content/uploads/2021/05/CMIS5p0.pdf) |
5661

57-
# Problem Definition
62+
### About This Manual
63+
This is a high-level design document describing the way to apply custom SI settings for CMIS supported modules.
5864

65+
## 1 Introduction and Scope
5966
Certain high-speed QSFP_DD, OSFP and QSFP modules require Signal Integrity (SI) settings to match platform media settings in order to achieve link stability, right tunning and optimal performance.
6067

61-
## Clause from CMIS5.0 spec for Signal Integrity
68+
### 1.1 Clause from CMIS5p0 spec for Signal Integrity
6269
Excerpt from CMIS5.0 spec providing definition of Signal Integrity:
6370

6471
![image](https://user-images.githubusercontent.com/115578705/236561523-8999b615-b271-4e28-9fbe-d0c9d414bdb8.png)
6572

6673
These SI settings can vary based on combination of the module vendor plus platform vendor. The module will have default TX/RX SI settings programmed in its EEPROM by module vendor, but platform vendor has provision to overwrite these settings to match their platform requirements.
6774
The host can apply new TX SI settings when TX Input Adaptive EQ is disabled for all TX Data Path lanes but RX SI settings can be applied directly. These TX/RX setting should be applied with Explicit Control bit is set to 1.
6875

69-
## Clause from CMIS5.0 spec for Explicit Control
76+
### 1.2 Clause from CMIS5p0 spec for Explicit Control
7077
Excerpt from CMIS5.0 spec providing definition of Explicit Control:
7178

7279
![image](https://user-images.githubusercontent.com/115578705/236561421-d960d243-cd26-4087-88fe-c621867ffaa7.png)
7380

74-
# Objective
75-
SI parameters can be vendor and module specific. The vendor can populate desired SI param values in a JSON file. Provide an approach in the CMIS state machine to generate and apply host defined SI parameters to module eeprom.
81+
## 2 Requirements
82+
This feature would be enabled per platform basis. If platform wants to use this feature, they would need to provide optics_si_setting.json file during init for XCVRD to parse it. The SI parameters can be vendor and module specific. The vendor can populate desired SI param values in a JSON file. Provide an approach in the CMIS state machine to generate and apply host defined SI parameters to module eeprom. The Modules that do not support CMIS and not part of CMIS state machine are not in the scope of this document.
7683

7784
![image](https://user-images.githubusercontent.com/115578705/236575703-aea7f377-ba5e-4e96-b18e-920f93e19774.png)
7885

79-
# Plan
86+
## 3 Architecture Design
8087
The SI media setting file optics_si_setting.json needs to be defined by each platform_vendor that will need SI settings. All SKUs of the platform will share the same optics_si_setting.json file. If no file is found, then this mechanism will be ignored.
8188

82-
This file will have TX, RX setting blocks, and each block will have two subblocks: the first is global level setting and the next is port level setting. These subblocks will eventually contain per-lane SI parameter setting values based on the type of vendor and speed that are expected to be programmed.
89+
This file will have TX, RX setting blocks, and each block will have two subblocks: the first is global level setting and the next is port level setting. These subblocks will eventually contain per-lane SI parameter setting values based on the type of vendor and speed that are expected to be programmed. The SI settings will not depend on cable length.
8390

84-
## TX_SETTING:
91+
### 3.1 TX_SETTING:
8592
This section will provide details on whether the TX EQ (TX input equalizer control) setting is FIXED or ADAPTIVE. Only adaptive EQ should be used for TX input, and it's enabled as the default setting in module. Fixed EQ is not recommended for TX direction and will not work until the SI/Hardware team explicitly recommends it.
8693

8794
If the EQ_FIXED flag is false or not present, then the SI param generation flow will come out of TX_SETTING and continue with the RX_SETTING block. But if the EQ_FIXED flag is true for TX_SETTING, then we need to disable AdaptiveInputEqEnableTx.
@@ -94,7 +101,7 @@ The TX Input EQ register control: Page 10h Byte 153 – 159
94101
| 154 - 155 | AdaptiveInputEqRecallTx1..8 (lane 1-8) |
95102
| 156 - 159 | FixedInputEqTargetTx1..8 (lane 1-8) |
96103

97-
## RX_SETTING:
104+
### 3.2 RX_SETTING:
98105
The RX_SETTING block contains the same sections as TX_SETTING, but the EQ_FIXED flag should always be true. The SI settings can be directly written and applied for RX output equalization.
99106

100107
The RX Output EQ register control: Page 10h Byte 162 – 173
@@ -105,25 +112,25 @@ The RX Output EQ register control: Page 10h Byte 162 – 173
105112
| 166 - 169 | OutputEqPostCursorTargetRx1..8 (lane 1-8) |
106113
| 170 - 173 | OutputAmplitudeTargetRx1..8 (lane 1-8) |
107114

108-
## GLOBAL_MEDIA_SETTINGS:
115+
### 3.3 GLOBAL_MEDIA_SETTINGS:
109116
This block's first level of identification will be the range of port numbers. The ports can be defined as a range of 0-31 or a list of multiple ports: 1, 2, 3, or a list of ports in the range of 5–10, 25–31, matching the index number in the port_config.ini file. This port range will have a unique defined lane speed, which will have unique vendor and vendor part number entries supporting this speed. Module key will be created based on speed and vendor details.
110117

111118
Each vendor will have per-lane SI param attribute entries applicable for the identified port + speed for the platform vendor. This value will be searched through the module key.
112119

113-
## PORT_MEDIA_SETTINGS:
120+
### 3.4 PORT_MEDIA_SETTINGS:
114121
The entries in this block will be unique single port numbers. The control of SI attribute list generation search will reach the PORT_MEDIA_SETTINGS block only when no attribute list is generated in the GLOBAL_MEDIA_SETTINGS block.
115122

116123
There will be unique speed and vendor/vendor_PN entries in each identified port block.
117124

118125
Default values can be platform defaults for multiple vendors in each section.
119126

120-
## List of standard TX/RX SI parameters
127+
### 3.5 List of standard TX RX SI parameters
121128
- SI_PARAM_TX_INPUT_EQ
122129
- SI_PARAM_RX_OUTPUT_PRE
123130
- SI_PARAM_RX_OUTPUT_POST
124131
- SI_PARAM_RX_OUTPUT_AMP
125132

126-
## Sample Optics SI setting file:
133+
### 3.6 Sample Optics SI setting file:
127134
```
128135
{
129136
“TX_SETTING”: {
@@ -137,32 +144,28 @@ Default values can be platform defaults for multiple vendors in each section.
137144
“GLOBAL_MEDIA_SETTINGS” : {
138145
“1-20”: {
139146
“100G_SPEED”: {
140-
“CREDO”: {
141-
“CREDO_PN”: {
142-
“SI_PARAM_RX_OUTPUT_PRE” : {
143-
“lane0” : “5”,
144-
“lane1” : “5”,
145-
“lane2” : “5”,
146-
“lane3” : “5”,
147-
“lane4” : “5”,
148-
“lane5” : “5”,
149-
“lane6” : “5”,
150-
“lane7” : “5”,
151-
}
147+
“CREDO -CAC82X321M2MC0HW”: {
148+
“SI_PARAM_RX_OUTPUT_PRE” : {
149+
“lane0” : “5”,
150+
“lane1” : “5”,
151+
“lane2” : “5”,
152+
“lane3” : “5”,
153+
“lane4” : “5”,
154+
“lane5” : “5”,
155+
“lane6” : “5”,
156+
“lane7” : “5”,
152157
}
153158
},
154-
“INNOLIGHT”: {
155-
“INNOLIGHT_PN”: {
156-
“SI_PARAM_RX_OUTPUT_POST” : {
157-
“lane0” : “8”,
158-
“lane1” : “8”,
159-
“lane2” : “8”,
160-
“lane3” : “8”,
161-
“lane4” : “8”,
162-
“lane5” : “8”,
163-
“lane6” : “8”,
164-
“lane7” : “8”,
165-
}
159+
“INNOLIGHT -T-DP8CNT-NCI”: {
160+
“SI_PARAM_RX_OUTPUT_POST” : {
161+
“lane0” : “8”,
162+
“lane1” : “8”,
163+
“lane2” : “8”,
164+
“lane3” : “8”,
165+
“lane4” : “8”,
166+
“lane5” : “8”,
167+
“lane6” : “8”,
168+
“lane7” : “8”,
166169
}
167170
}
168171
}
@@ -185,8 +188,8 @@ Default values can be platform defaults for multiple vendors in each section.
185188
}
186189
},
187190
“PORT_MEDIA_SETTINGS” : {
188-
“32”: {
189-
“EOPTOLINK”: {
191+
“32”: {
192+
"100G_SPEED": {
190193
"Default": {
191194
“SI_PARAM_RX_OUTPUT_PRE” : {
192195
“lane0” : “9”,
@@ -205,7 +208,7 @@ Default values can be platform defaults for multiple vendors in each section.
205208
}
206209
```
207210

208-
# Proposed Work-Flow
211+
## 4 High-Level Design
209212
Please refer below points in line with flow diagram.
210213

211214
1. When CMIS-supported module insertion happens in XCVRD, the module will progress to the AP_CONFIG state (after DP_DEINIT state) in the CMIS state machine. During which, when the module is in DataPathDeactivated or Disabled state, check if the optics_si_setting.json file is parsed successfully and if lane speed needs special Signal Integrity (SI) settings.
@@ -244,12 +247,21 @@ SI attribute generation flow:
244247

245248
![Untitled](https://github.com/AnoopKamath/SONiC/assets/115578705/92e0291d-8d76-4d20-a535-95ee30a9265e)
246249

247-
# Feature Enablement
248-
This feature would be enabled per platform basis. If platform wants to use this feature, they would need to provide optics_si_setting.json file during init for XCVRD to parse it.
250+
## 5 SAI API
251+
There are no changes to SAI API
252+
253+
## 6 Configuration and management
254+
There are no changes to any CLI/YANG model or Config DB enhancements.
255+
256+
## 7 Warmboot and Fastboot Design Impact
257+
There is no impact to Warmboot and Fastboot design. This feature is invoked as part of exisiting CMIS manager flow only
249258

250-
# No Transceiver Present
259+
## 8 Restrictions or Limitations
251260
If transceiver is not present:
252261
- All the workflows mentioned above will not invoke
262+
Modules that do not support CMIS and not part of CMIS state machine are not in the scope of this document.
253263

254-
# Out Of Scope
255-
Modules that do not support CMIS and not part of CMIS state machine are not int he scope of this document.
264+
## 9 Unit Test cases
265+
1. Check XCVRD/CMIS log if optics SI settings are succesfully applied for module which expect the SI settings.
266+
2. Check XCVRD/CMIS log if optics SI settings are ignored for modules that dont expect the SI settings.
267+
3. Validate no link flaps or link down once SI settings are applied

0 commit comments

Comments
 (0)