[WIP] Bits and Registers #13860
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[WIP] Bits and Registers #13860
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Co-authored-by: Jake Lishman <[email protected]>
- Use `macro_rules!` to create `Bit` and `Registers`.
- Add `new_owned` method for `BitInfo`.
Pull Request Test Coverage Report for Build 13479642251Warning: This coverage report may be inaccurate.This pull request's base commit is no longer the HEAD commit of its target branch. This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.
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- Rebalance currently available api to allow for superclasses `Bit` and `Register` to also live in Rust. - Remove: `ShareableBit` triat and structs that implement it. Replace them with new structs.
- Add prefix class attribute for python `Register` instances.
- Add `BitExtraInfo` as a soft identifier for `BitInfo`, can be null to identify a `Bit`. - Add `RegisterInfo::get` method to retrieve the information of a `Bit`. - Have the rust registers own their counters instead of having them be Python exclusive. - Make subclassing of `Regster` and `Bit` a bit more effective by helping the subclasses inherit most methods.
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…GCircuit`. - Modify `BitData` to accept an extra generic value specifying a "sharable" object type that can also be turned into a `PyObject` to allow for compatibility with `Var`. - Rename `BitAsKey` to `VarAsKey` as it is currently only used for `Var` instances. - Modify methods in `CommutationChecker` and `GateDirection` passes to use the newer methods. - Other tweaks and fixes.
…bit`. - Remove imports of `QUBIT` and `CLBIT` from `DAGCircuit` and `CircuitData`.
- Discarded old equality and hashing methods for `PyBit` and `PyRegister`. - Fix `replace_bits` to accept any iterator over `Qubits` and `Clbits` from Python. - Add `is_empty` methods to Register data, wherever `len` is available. - Add additional parsing during creation of `Register` to more closely match previous behavior. - Modify `Bit` tests due to mocking no longer operating correctly.
- Add method `register` to `BitData` to better represent a register reference in an owned bit.
- Add missing quotation marks in `Register` repr().
- Bits and registers that live in Rust are not guaranteed to pass the `is` equality check in Python. - Restore type checking in `DAGCircuit` when adding bits.
- `Bits` should retain their hash value upon deserialization to avoid incorrect retrievals via hash or indexing. Fixed by implementing correct `__reduce__` method in `PyBit`, `PyClbit`, and `PyQubit`. - Replace `__getnnewargs__` methods with `__reduce__` for more versatile serialization. - Extend `SliceOrVec` to include a method that allows a vec with negative indices to correctly iterate based on a provided size. - Modify `FullAncillaAllocation` to not replace the `QuantumRegister` prefix. - Add `instances_count` getter attribute to all registers. - `is` comparisons are no longer guaranteed to work between bits and registers. So some tests have been modified to reflect that. - When `apply_operation` in the `DAGCircuit` receives a clbit in place of a qubit and viceversa, it will throw a type error, not a Key error. This is handled by PyO3 directly during extraction.
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- Create `RegisterData` struct which, similarly to how `BitData` works, stores the registers and allows to access them by key, in this case by name or index. - Tweak `CircuitData` and `QuantumCircuit` api to allow for access of registers from within `CircuitData`. - Add `qubit_indices` and `clbit_indices` structs to keep track of the locations of bits and registers within the circuit. - Modify `circuit_to_dag` to obtain the registers directly from `CircuitData`. - Modify `BlueprintCircuit` to rely on `CircuitData` to access `QuantumRegister` instances. - Add setters and getters for registers. - Modify `circuit_to_instruction` to bring over the registers into the definition of the `Instruction`. - Add `contains` method to `BitData`. - Add rust native `BitLocations` that can be converted to a `Python` version if needed.
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Summary
Bits and registers in Rust (Part 2)
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